Design Verification
Functional verification using SystemVerilog and UVM, with constrained-random simulation and formal verification techniques.
Full Syllabus
What you'll learn
From RTL and language fundamentals through UVM methodology and debug.
Foundations & Language
✓Digital design and RTL fundamentals refresher
✓Verilog basics for verification engineers
✓SystemVerilog data types, classes and interfaces
✓Object-oriented programming concepts for verification
✓Verification planning and test plan documentation
Verification Flow & Methodology
✓UVM architecture — sequences, sequencers, drivers, monitors
✓Constrained-random stimulus generation
✓Functional coverage and coverage-driven verification
✓SystemVerilog Assertions (SVA) for protocol checking
✓Scoreboards, reference models and self-checking testbenches
✓Regression management, debugging and waveform analysis
SystemVerilogUVMFormal